There is one good question we hear from time to time from our Customers. Is it important to place decoupling capacitors close to the destination IC? The general rule of thumb says so, and every PCB designer knows it, even less experienced.
However, in the real-life practise of routing it is often quite difficult to find an acceptable compromise between mechanical restrictions and electrical necessity. Especially if we say not about a couple of simple chip capacitors or about a low-power rail. What if it is an FPGA or PHY in BGA package with 50-100 decoupling capacitors?
Just recently our engineers were dealing with a complex PCB project, which, among other things, presented such an unexpected challenge. There was a 10G Ethernet PHY with 60 decoupling capacitors on the board. The layout designer tried to make the highest quality design possible and he managed to put almost all the capacitors very close to the corresponding pin of the IC on the back of the board. But not all of them. In such cases, capacitors of smaller package and capacitance are usually placed directly nearby the pin and slightly larger capacitors are a bit further, but as close as the situation on the board allows. So here is how the problem was solved in the given project:
So far the layout looks fine. However, during the Power Integrity analysis of one of the power sub-nets, it became clear that the impedance curve for this circuit is significantly higher than the target impedance at low frequencies. This indicates a lack of “large” high-capacitance decoupling capacitors. The curve is shown here:
This situation could cause problems with the Ethernet PHY power supply unit. Analyzing this issue, it was decided to slightly re-do the PCB placement and move the only large capacitor to one of the three pins of this sub-net.
Along with a little change in the capacitance of a couple of small capacitors to suppress the second peak, this measure led to a significant result improvement, see the next diagram:
Even in this one board, a few other issues like described above were found. The example considered in this article is just a special case, clearly demonstrating the unconditional need for Power Integrity analysis for boards with high-end ICs such as FPGA or PHY, as well as for boards with high currents flowing in order to avoid problems on real samples.
Also, we would like to emphasize that in real designs, even executed in strict accordance with the manufacturer’s recommendations, various deviations are possible that are simply impossible to predict without proper SI/PI simulations.