‘Everything is changing. Designing electronics 10 years ago and now has a big difference and needs new methods and approaches today. The things that before could be stayed without attention can’t be ignored anymore.’ – we many times read this in numerous articles and guidelines. Probably, everyone already understands this, as well as the necessity of Signal integrity and Power integrity analyses! But most of the companies still don’t know how to put the analyses in the project scope, because of the tight schedule for PCB design and absence of Signal integrity specialists in a team.
In a practice, the whole responsibility for board design lays on the shoulders of a PCB engineer who must follow the consistent implementation of multiple rules of thumb from layout guidelines. But layout guidelines can’t cover all possible variants of the board design and describe only one certain case which normally differs from yours. The current article gives one interesting example of simulation helped to find a problem in the fully routed PCB.
One of our customers addressed a problem with a malfunctioning DDR4 memory interface. Due to cost savings needs, the customer set an ambitious goal to build a printed circuit board on a stackup with as few layers as possible.
Our engineers began to analyze the board. First, a general PCB review and basic Signal integrity and Timing analyses were performed, which did not reveal any critical errors in the interface. The waveforms were perfect, without overshoots and ringing. An example can be seen below.
Since the printed circuit board was made on a 6-layer stackup, where layer 2 was used as a Power and layer 5 as a Ground, it was decided to perform a more detailed analysis of the signals taking into account the PDN system, the so-called SI/PI co-simulation. The result of the analysis was that the waveform for some circuits had a strong distortion (red).
A Plane-noise analysis which also performed during SI/PI co-simulation helped us to find the reason for the problem. The maximum noise in the power plane was exact at the point where traces jumped from one layer to another, then the noise propagated along the plane until it encountered with by-pass capacitors. This called us back to the layout review again.
And indeed! A more detailed study of the layout revealed that some of the circuits had an extended section of the trace on the outer layer 1, which had Power supply as the reference layer. However, the signals transferred to layer 4, where the GND was the reference. This was the reason for excessive plane noise in the position of the signal via. Thus, the PCB engineer unexpectedly created a split in the return current path.
In addition, for traces that were closer to the edge of the reference plane, the waveforms were significantly worse than those that were closer to the processor. But why it was so? The thing was in the arrangement of by-pass capacitors which in that case served as stitching capacitors and created continuous return current path.
There are several options for solving this problem: adding two more Ground/PWR layers and stitch them by vias, placing stitching capacitors near the signal vias or even partially re-layout memory interface in order to exclude the change of reference layers. The choice of the most optimal solution is not always obvious because of a variety of factors. Anyway, all of them mean correction the board and requires additional time and one more production spin round. What would you choose? We would definitely prefer to do Signal integrity analysis in the stage of PCB layout and thus eliminate these problems before production.
The PCB engineer coped with this task perfectly and kept in 6 layers, where layers 1, 3, 4 and 6 were signal, and layers 2 and 5 were power/ground planes.