Professionals working with schematic and PCB designs know that noise ripple in a power distribution network (PDN) is one of the most harmful things for an electronic device. Getting an inoperative device from the first start is real here. But the worst possible case is to find a problem while thousands of units are already made and some of them are failing due to excessive ripple in the PDN. So, how to avoid any harm from noise ripple in a PDN? Options are there!
The first thing to think of is reducing current consumption, though this suggestion may not be applicable if the design is already power-optimized. So then reducing the PDN impedance may become a nicer alternative. Edality’s experience shows that this strategy can be successfully implemented by applying strict principles of precise PCB layout design. Nevertheless, for both strategies, it must be said that without conducting an analysis we cannot be completely sure that the noise level in a certain power net for a particular IC will not exceed the level allowed by the manufacturer.
Regardless if a hardware designer and a PCB designer have done their best in a design or they have not, sometimes we can still see pictures like those that are shown below when a new PCB layout comes for examination after the prototype had failed:
On the pictures above we can see the PDN impedance curves of specific voltage rails that exceed the calculated target impedance line for specific chips. It means that the requirements of the chip manufacturer to ensure a certain noise level (usually 3-5% of voltage) for specific interface and respectively frequency range have not been met. The first thing we begin to analyze in cases like this one is the layout quality, putting special attention on a problematic voltage rail. It happens that a possible issue source can be determined immediately. Just like in the picture below, where a slack of ground vias causes high interconnects inductance.
The inductance of decoupling capacitors interconnects is a highly important question. From the basics of electronics, it is well-known that reducing this inductance may be reached first by placing decoupling capacitors as close as possible to the destination pins of an IC. The perfect location for them is right under ICs pins on the opposite side of the board. However, it is often not possible because of the components’ dimensions. If so, we recommend reducing the inductance of their connection to the internal planes. A very good idea here is to use via in pad technique, but if this approach is not available as well, routing 271 shown below will be preferred, i.e. usage of wide tracks and minimum distance to a via is needed.
If the problem is implicit and difficult to determine by visual analysis, it is time then to consider improving the design with additional capacitors and increasing the area of planes for a troublemaking voltage rail. Oftentimes this way of PCB optimizations can be time-consuming and not cheap. So, for dense electronic boards, we consider the possibility of using the same size capacitors of alternative capacity without layout changes as a primary option. For instance, the following PDN impedance improvement (green line) was obtained only by replacing 4 capacitors 0.22uF 10V by 1 uF 10V and 4 capacitors 0.47uF 6.3V by 4.7 uF 6.3V. Having these corrections in place would be extremely problematic without using decoupling analysis.
The experience of Edality counts years of having real practical cases. We clearly see how important it is to add appropriate analysis as early in the design cycle as possible to keep R&D cost-effective and shorten time to release. Having electrical analyses as a mandatory part of the development cycle is real insurance in the world of electronics reducing the number of surprises as the design progresses.