Nowadays, with each subsequent analysis, we and our customers become more and more convinced of how important to perform the Power Integrity (PI) analysis of a PCB with high currents flow. Today we would like to unveil one of the many possible Power integrity issues that your design may contain and which you do not suspect. This issue is called Max Via current.
More recently, we performed an analysis of a complex 12-layer board with two DDR4 channels and Xilinx FPGA onboard. There were several voltage rails on this board with fairly high power consumption. During the simulations of one of the voltage rails, we noticed an interesting finding:
The calculated current passing through 200um via was exceeding 2 Amps, which could easily lead to serious problems after production. The strangest part was the fact that this via was the connection point of the decoupling capacitor. So, we had to go deeper into the layout details to find out what was the root of the problem.
After spending a few hours more working with the layout we noticed that the current transfer of this power rail was formed by polygons on several different layers. Apparently, the PCB engineer planned that a massive plane on one of the layers will supply main sinks, and an auxiliary one will supply low-current power points. Alas, it turned out that for a significant part of the current it became easier to flow along the auxiliary polygon and join the general flow through this one small 200um via.
The best (and the simplest) solution of the problem we could suggest in this particular case was adding a few additional vias in the area of the overloaded via. After adding specifically three additional vias, the current per via on the cross-linking area of 2 polygons dropped below the value of 1A.
Can we call it a mistake in PCB layout? Probably yes. However, it is often difficult to predict the current behavior and its distribution on the board, especially if you do not have enough experience in Power Integrity. This only emphasizes the undeniable need in Power analysis to identify and prevent possible errors at the PCB design stage, when it still does not entail financial losses.