Imagine after covering all the known requirements you are getting close to the final step of your PCB design. But suddenly you feel doubts if your board may function as it is supposed to. Then you start recalling all the things that still can go wrong — did I make any mistakes during routing? Did the initial specification requirements where copied mistakenly from another project with no changes? How good was the reference design that I’ve used? Sometimes it is just so hard to feel confident about delivered PCB.
Indeed, very often engineers must read through long specifications from different IC manufacturers to get ready for routing. When the electronic board is big there is simply no time for that, the best available option is to copy data from reference designs. Doing that means replicating same errors from one design to another. Furthermore, reference designs often require using advanced manufacturing technologies with a non-optimal stack-up and a number of layers that will finally increase production cost a lot. And partial customization of a reference design when you need let’s say to change board outline or I/O configuration, may bring new errors.
Signal Integrity (SI) and Power Integrity (PI) analyses are a solid and proven solution for the cases when high quality of a design is really sought. One of the examples showing a typical use case is described below.
Solving DDR4 issue with help of Signal Integrity analysis
Some time ago while performing one of the projects the team of Edality faced a typical, as it seemed at first sight, task. We had to develop a layout with four DDR4 chips controlled by one FPGA with one small remark: memory chips had a doubled die in each package and therefore overall load capacitance implicitly doubled as well. Layout guidelines for FPGA recommended to route address/cmd/control bus in a traditional Fly-by topology. However, the very first pre-layout study indicated that signals did not have required waveforms, they are shown in the image below. The worst-case Eye diagram indicated multiple threshold crossing, meaning serious violations. In other words, it became clear that the board won’t work.
Traditionally, routing DDR/DDR2 memory was the most complex part of PCB design. It required making a T-shape topology with precise signal lines lengths matching for address/cmd/control group. And that was very time-consuming! Then DDR3/DDR4 memory chips came to the market and they required Fly-by topology style with daisy-chain connection. It simplified the development process for PCB designers because the required labour effort decreased. But still, the new routing approach is not always working better than the old one, and the present use case clearly demonstrated it.
Signal Integrity analysis allows to check various predefined configurations of a PCB and then compare the quality of output signals visually. To improve signal waveform in this exact case, engineers of Edality performed six experiments one after another and came up with a detailed report suggesting the best setup for the current design. What surprised the most is that the best results fitting to the initial expectations were achieved by using T-shape topology typical for DDR2, but with 2-point termination! As shown below, the timing diagram and Eye diagram looked just perfect.
In sum, Signal Integrity analysis helped to avoid problems with the device on a later stage, when an expensive electronic board could be produced and assembled. The price of such an issue grows exponentially on every new stage of the product development cycle. And the fact of finding such problems in third-party designs so often means that SI and PI checks should become a mandatory part of electronics design. If you still want to feel confident about every PCB topology developed, of course.