When doing Signal Integrity analysis for different interfaces, our team often faces various challenges depending on many factors such as the selected topology, stackup, PCB layout, driver and receiver models. And as practice shows, not always the initial solution that was chosen by a Customer can ensure the successful operation of a real device in the future.
The DDR interface in general and DDR4, in particular, is still a very popular interface for SI analysis. Recently we analyzed another design with DDR4. As it is known, for DDR4 the FLY-BY topology normally used for Command/Address/Control lines. In this design, everything was done by the PCB designer as it should be, the fly-by technology was used and lines were length matched relative to the clock for each DDR chip. In general, the topology looked as follows:
A surprise came from the driver model. The rise time of the CPU clock buffer was extremely small, near 50 ps. As a result, we could obtain the following clock eye diagram:
The signal was very dangerously close to the thresholds and such a situation, with the additional influence of power supply or due to production tolerances, could easily lead to timing errors. The lack of even a minimum margin is always bad.
After analyzing the situation, we tried to minimize the effect of via stubs when connecting DDR chips to the transmission line, namely, to move the clock traces segments between DDR4-1 and DDR4-2 and between DDR4-2 and DDR4-3 from layer 8 to layer 3, as well used microvia 2-3 to connect DDR4-2 and DDR4-3, thereby bringing the fly-by line as close as possible to the chips. The corrected topology looked like it is shown below:
As a result of these manipulations, it was possible to improve the clock waveform to such a state:
This case can clearly demonstrate the influence of the via stubs on the signal form. With such a clock it is not at all risky to send the board to production.
Of course, such an improvement is not applicable to every design, it can be banal even because it is impossible to use microvia. In the given case, this was the best option in terms of resource consumption.
However, there are a number of other ways we can improve DDR4 based design to avoid data transfer errors in our arsenal. Please contact us to get a free quote on running Signal Integrity simulations!