Professionals working with schematic and PCB designs know that noise ripple in a power distribution network (PDN) is one of the most harmful things for an electronic device. Getting an inoperative device from the first start is real here. But the worst possible case is to find a problem while thousands of units are already made and some of them are failing due to excessive ripple in the PDN. So, how to avoid any harm from noise ripple in a PDN? Options are there!
Nowadays, with each subsequent analysis, we and our customers become more and more convinced of how important to perform the Power Integrity (PI) analysis of a PCB with high currents flow. Today we would like to unveil one of the many possible Power integrity issues that your design may contain and which you do not suspect. This issue is called Max Via current.
‘Everything is changing. Designing electronics 10 years ago and now has a big difference and needs new methods and approaches today. The things that before could be stayed without attention can’t be ignored anymore.’ – we many times read this in numerous articles and guidelines. Probably, everyone already understands this, as well as the necessity of Signal integrity and Power integrity analyses! But most of the companies still don’t know how to put the analyses in the project scope, because of the tight schedule for PCB design and absence of Signal integrity specialists in a team.
Imagine after covering all the known requirements you are getting close to the final step of your PCB design. But suddenly you feel doubts if your board may function as it is supposed to. Then you start recalling all the things that still can go wrong — did I make any mistakes during routing? Did the initial specification requirements where copied mistakenly from another project with no changes? How good was the reference design that I’ve used? Sometimes it is just so hard to feel confident about delivered PCB.
