In an era of compact design and higher clock speed rates signal integrity is an ever increasing concern for high speed digital design. For any high speed design it is very important to do the signal integrity analysis.
Signal integrity allows additional verification of high-speed signals on the printed circuit board (PCB) at the designing stage, which significantly reduces the number of extemporaneous errors in the finalized product, also reduces the time for testing and debugging and putting the product earlier on the market. One of main advantage of Signal Integrity is that this type of PCB analysis can be easily integrated into the standard designing process of any product without significant delays.
There are two stages of PCB analysis from the SI perspective: pre-layout and post-layout. Pre-layout allows you to analyze the board at an early stage of design – this eliminates the possibility of relayout in the later stages, and also helps to choose board stackup, which will be optimal in terms of performance and cost, which is an indisputable advantage in a competitive environment.
Post-layout analysis is done in the later stages of design. It allows modeling high-speed interfaces, given the final configuration of the PCB, which includes the parasitic properties of the conductors in the selected stackup, as well as the interaction of the conductors with each other (Crosstalk). Timing analysis for any parallel bus, such as memory DDR, can only be done on the Post-layout, when all bus conductors are routed and length matched in groups.
Edality is a leading signal integrity analysis and consulting company, helping our customers throughout the whole PCB design process. We perform sophisticated layout examination to ensure that all critical layout guidelines are met. As a result of our work we provide a detailed SI report with recommendations for increasing the quality of your device. If we find issues during the analysis process, we provide instant feedback and advice so the problems can be quickly resolved.