Go to Edality BV
DFM/DFA
1st Final Design
Analysis Report
Edality BV
Haaksbergerstraat 67
7554 PA Hengelo (ov)
The Netherlands
Phone: +31 74 2555780
Fax: +31 74 2555780
Email: info@edality.com
URL: www.edality.com

Report results created with Mentor Graphics Valor NPI © release 110

Report created at: 18-05-21
Report created by: baan


Customer: Example Product name: Example
Product partnumber: NA Product version/issue: 1
Board technology: rgb_cib_bv_12_1600_01_90_100_85_100_250_150_125 No. of physical board layers: 12
Trace width and clearance: 100 µm No. of pressfit parts found: None
No. of top side components: 337 No. of bottom side components: 385
No. of board nets: 720 Board thickness: 1600 µm
Total no. of shorts found: 0 Total no. of open nets found: 0
Soldering process defined: Reflow-Selective Wave No. of tooling holes assigned: NONE DEFINED!
No. of mounting holes assigned: Total number of testpoints defined: NA
No. of testpoints placed on the top side: NA No. of not to be placed components: 0
No. of WS pads on RFS top side found: 0 No. of WS pads on RFS bottom side found: 0
No. of RFS pads on WS bottom side found: NA Total no. of board fiducials assigned: 6
Total no. of component fiducials assigned: NONE DEFINED! Units of measure: micrometer
No. of matched VPL packages: 48 Did board pass the 1st Final Design analysis: No, see Result(s)
Notes/Remarks: None


Go to Sintecs BV Associated and attached documents: Netlist Analyzer results report
  Printable report in pdf format
Not matched VPL parts
Nets without ICT Testpoints report


Result(s) Overview

No.
Issue
Category
Layer
X loc.
(mm)
Y loc.
(mm)
Value found
(µm)
Value expected
(µm)
Image
1Please increase this clearance.cad_self_spacingsignal_1_hf023.775-32.23775100
Click on image to enlarge
2Please increase these clearances.cad_self_spacingsignal_8_hf274.375-39.8132599.9
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3Please fix these coverage situations.coveragesmt21.500-65.1755074.9
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4Please increase this clearance.coveragesmt40.400-47.4857074.9
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5Please increase this clearance.coveragesmt37.530-96.69570.14774.9
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6Please increase this clearance.coveragesmb53.155-76.17570.84274.9
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7Please increase this clearance.nfp_pos_spacingsignal_7_pwr62.000-59.71961.13100
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8There are no pads for pins (connector X1000). Is this allowed?no_pad_for_pin;
_ES
comp_+_top95.748-102.345200!!!
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9There is no pad for pin (connector X1000). Is this allowed?no_pad_for_pin;
_ES
comp_+_top101.248-102.345200!!!
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10Please increase this clearance.npth2csignal_8_hf218.565-22.380430500
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11Please increase this clearance.npth2csignal_10_hf38.804-18.825452.477500
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12Please increase this clearance.npth2psignal_10_hf311.478-19.535471.3500
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13Please increase this clearance to at least 100 um.p2csignal_12_hf445.550-75.25099.3124.9
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14Please increase this clearance.p2csignal_10_hf326.300-61.85099.0899.9
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15It is preferred to have a minimum plane to plane clearance on P/G layers of at least 200 um. Please fix.plane_spacingsignal_6_pwr14.471-103.193120199
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16It is preferred to have a minimum plane to plane clearance on P/G layers of at least 200 um. Please fix.plane_spacingsignal_7_pwr31.200-39.275150199
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17Please increase this clearance.self_spacingsignal_12_hf424.082-88.43636.252100
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18Please increase this clearance.self_spacingsignal_12_hf434.525-20.37550100
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19Please fix this sliver situation.short_sliversignal_12_hf451.738-34.43836.2150
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20Please fix this sliver situation.short_sliversignal_12_hf435.505-47.71275150
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21Please fix this sliver situation.sliversignal_1_hf044.684-16.46231.45150
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22Silkscreen on the top of the board looks strange. Please verify.ss2smsst93.750-14.1250150
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23Please remove this stubbed buried via.stubbed_buried_viad_2_1117.175-31.3252003
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24Please remove this stubbed via.stubbed_viasignal_12_hf436.800-47.6002003
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25Please remove this stubbed via.stubbed_viasignal_12_hf437.600-47.6002003
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26Please remove this surface stub.surface_stubsignal_12_hf413.508-30.9551000.77!!!
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27Please remove this surface stub.surface_stubsignal_12_hf436.357-43.968556.937!!!
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28Please balance the connected tracewidths per pad for the following parts (100 um via in pad is equal 157 um trace width): R2008 R6001 R4020 R4021 R6045 R6046 R6043 R6049 R6003 R2000 R2014 R6034 C4066 R5003 R4003 R5004 R4010 R4008 R4001 R4011 R4014 C5006 C2071 C4042 C6093 R6059 C6109 R6061 C6111 R6060 C6110 R6069 R6065 R6066 C6112 R6067 C6103 C6082 R4007 R4 R2037 C6095 C2084 C2078 C2065 C6080 C2066 C2060 C2093 C2080 C6100 C2070 C6102 C4055 C2087 C4034 C2081 C2067 C2077 C2094 C4035 C2079 C6094 C2061 C2074 C6079 C2059 C2088 C2097 C2068 C2086 C2092 C6107 C6081 C6086 C2095 C2064 C6083 C2085 C2090 C2083 C2096 C2091 C4044 C6096 C6087 R6047 C2063 C2069 C6098 C6101 C6078 R6048 C2073 C6097 C2089 C2082 C4032 C4038 C4043RFS:
trace_width_ratio;
disc0402
signal_12_hf454.575-79.000109.952.07
Click on image to enlarge
29Please balance the connected tracewidths per pad for the following parts (100 um via in pad is equal 157 um trace width): C6008 R2010 R2009 C6055 C6000 C6007 C6022 C6036 C6056 C2017 C6012 C6003 C2023 C2019 C2020 C2021 C6018 C2016 C6017 C6006 C6019 C2018 C6033 C2022 C6016 C6057 C6062 R6030 C2015 C2014 C6005 C6063 C6014 C6001 C6013 C6066 C6067 C2031 C2024 C6052 C2009 C2025 C1016 C2000 C6053 C2001 C2058 C4060 C2053 C6061 C2011 C2026 C2002 C7000 C6054 C2030 C2012 C2052 C2028 C6002 C6004 C7005 C2055 C2008 C6021 C4061 C2032 C2051 C2033 C2034 C2035 C2003 C7006 C6010 C2036 C7001 C2004 C2037 C1011 C2007 C4062 C2038 C7007 C7002 C6011 C2041 C2039 C6009 C2006 C2013 C2042 C2043 C1015 C1010 C2044 C2057 C6059 C4063 C2045 C6058 C6035 C6060 C2075 C4028 C5008 C7004 C5001 C1013RFS:
trace_width_ratio;
disc0603
signal_12_hf429.475-40.40095.2552.07
Click on image to enlarge